• Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration [Best Paper Award]
    Neha Karanjkar, Madhav Desai
    Proceedings of the 12th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2022), July 2022, Lisbon, Portugal
    pages 142-150 ISBN: 978-989-758-578-4
    [link] [pdf]

  • Mixed Discrete-Continuous Simulation for Digital Twins
    Neha Karanjkar, Subodh Joshi
    Proceedings of the 11th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2021), June 2021, Online
    pages 422-429 DOI: 10.5220/0010580804220429 ISBN: 978-989-758-528-9
    [link] [pdf]

  • A SimPy-based Simulation Testbed for Smart-city IoT Applications: Poster Abstract
    Neha Karanjkar, Poorna Chandra Tejasvi and Bharadwaj Amrutur
    Proceedings of ACM/IEEE Conference on Internet of Things Design and Implementation (IoTDI 2019), April 2019, Montreal, Canada.
    [link] [pdf]

  • A Simulation-based Technique for Continuous-space Embedding of Discrete-parameter Queueing Systems
    Neha Karanjkar, Madhav Desai, Shalabh Bhatnagar
    Proceedings of the 32nd annual European Simulation and Modelling Conference (ESM 2018), Ghent, Belgium.

  • Digital Twin for Energy Optimization in an SMT-PCB Assembly Line
    Neha Karanjkar, Ashish Joglekar, Sampad Mohanty, Venkatesh Prabhu, D. Raghunath and Rajesh Sundaresan
    Proceedings of the IEEE 2018 International Conference on Internet of Things and Intelligence Systems (IoTAIS 2018), Bali, Indonesia.

  • An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems using a Novel Simulation Based Interpolation Technique
    Neha V. Karanjkar and Madhav P. Desai
    Proceedings of The IEEE 2015 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2015), Atlanta, USA. Pages: 85-88


  • A Python-based Mixed Discrete-Continuous Simulation Framework for Digital Twins
    Neha Karanjkar, Subodh M. Joshi
    To be published in Springer Lecture Notes in Networks and Systems (LNNS)

  • On Continuous-space Embedding of Discrete-parameter Queuing Systems
    Neha V. Karanjkar, Madhav P. Desai, Shalabh Bhatnagar
    Online: arXiv:1606.02900
    [arXiv link]

  • A Scalable Approach to Simulation Optimization of Multi-core Systems over a Discrete Parameter Set
    Neha V. Karanjkar, Madhav P. Desai
    Online: arXiv:1411.2222
    [arXiv link]

  • Comments on “Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing”
    Neha V. Karanjkar, Rasmi R. Sahoo, and Maryam Shojaei Baghini
    IEEE Transactions on VLSI Systems 18(9):1381-1383, 2010


  • Industrial IoT for Energy-efficient Assembly Lines
    Cyber-Physical Systems Symposium (CyPhySS) IISc Bangalore, July 2018 [pdf]

Talks and Workshops

  • Introduction to Discrete-Event Simulation
    Tutorial organized via ACM Goa Professional Chapter, November 2021 (link to poster)

  • Review of architectural features for supporting program execution
    One-day session in ACM India Online Summer School on Program Execution, June 2021 (link)

  • Simulation Tools for the Internet of Things
    Session in ATAL FDP on Internet-of-Things Architecture and System Design at IIT Goa, Nov 2020 (link)

  • IoT-enabled Maritime Applications
    Short talk as part of the CEFIPRA-Goa-Atlantic workshop at Brest, France. Jan 2020

  • SimPy for Discrete-event Simulations
    Invited talk at Debutsav (a conference on FOSS by the Debian community) Sept 2019

Ongoing and Past Projects

Sitar (Simulation Tool for Architectural Research)

  • [Project Webpage] [Introductory Paper on Sitar]
    Sitar is a framework for modeling and simulation of discrete-time systems (such as discrete time queues, computer networks and computer architectural models). It consists of a system description language and a cycle-based simulation kernel. The language allows a system to be described in a hierarchical manner as an interconnection of modules running concurrently. The behavior of each module can be described in an imperative manner using constructs such as time-delays, conditional wait statements, fork-join concurrency, and branch/loop constructs. C++ code can be embedded in a module description in a straightforward and well-defined manner. The sitar language parser has been written using Antlr V3. The simulation kernel is lightweight, consisting of a small set of C++ classes, and has been parallelized using OpenMP.

A Framework for Simulation of the Device Layer in Smart City IoT Stacks

  • As part of a smart-city project at RBCCPS, IISC Bangalore, the aim was to develop a scalable and flexible framework for the simulation of the device layer in smart-city applications. An abstract based on this work was published in the IoTDI 2019 conference.
    (August 2018 - Dec 2018)

Discrete-event modeling for Industrial IoT applications

  • As a part of an Energy-efficient assembly lines project at RBCCPS, my work involves building simulation models of the assembly line for prediction, optimization and real-time monitoring in an industrial Internet-of-Things framework. An open-source simulator for an SMT-PCB assembly line with GUI support, developed as a part of this project is available here.
    PI: Prof. Rajesh Sundaresan, IISc Bangalore
    (August 2017 - August 2018)