A Modeling and Simulation Framework for Synchronous Discrete-event Systems

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Sitar is a framework for modeling and parallel simulation of synchronous discrete-event systems in application domains such as networks, computer architecture models, clocked digital systems, and discrete-time queueing networks. It consists of a system description language and a lightweight simulation kernel. A system is described as a set of concurrent, interconnected modules operating on a global clock. The language supports hierarchical descriptions: modules can contain instances of other modules. The behavior of each module can be described in an imperative manner as a sequence of statements. The language supports constructs such as :

  • Time delays
  • Fork-join Parallel blocks
  • Branch/loop constructs
  • Procedures and
  • Code blocks (instantaneous)

In addition, C++ code can be embedded into a module description in a straightforward and well-defined manner. Each module description gets translated to a C++ class. The generated code can be compiled and linked together with the simulation kernel to get a single simulation executable. The simulation kernel consists of a small set of C++ classes, and supports parallel execution using OpenMP. The simulation uses a two-phase algorithm for deterministic execution : each clock cycle is divided into two phases, and input/output events are restricted to separate phases.

Sitar can be used for modeling discrete-event systems such as computer-architectural models, communication networks and discrete-time queues. It is written for Linux.