CS 210 Digital Systems Design (Autumn 2021)


This is a core course for second-year undergraduate students in Computer Science and Engineering.
The course will be conducted in an online mode.

  • Course Credits: 4

  • Lectures: 3 hours a week

  • Lab: 3 hours a week

Course Objectives

  • Understand the key principles underlying the design of Digital Systems

  • Gain practical skills in designing and building complex digital systems using HDLs and modern tools

  • Understand how various digital system modules fit together to make a basic computer.

Timings

  • Mondays 2pm-3pm

  • Wednesdays 3pm-4pm

  • Thursdays 4pm-5pm

  • LAB: Tuesdays 3pm-5pm

Google Classroom will be used for all class notifications and discussion.

Course Textbooks

  • Digital Design with an introduction to the Verilog HDL (5th edition or 6th edition)
    by M. Morris Mano and Michael Ciletti

  • Free Range VHDL (Online book freely available here)

Reference Books

  • Digital Design: Principles And Practices (4th Edition)
    by John F. Wakerly

  • The VHDL Cookbook
    by Peter J. Ashenden (Online book freely available here)

  • VHDL: Programming by Example
    by Douglas Perry

Video Lectures

Video tutorials for the Autumn 2020 CS 210 LAB are available on YouTube. (Link to Youtube Playlist)

Course Contents and Lecture Plan

  • Module 1: Introduction to the design of Digital Systems: the What, Why and How

  • Module 2: Number Systems and Binary Numbers

  • Module 3: Boolean Algebra, Logic Gates, Gate-level Minimization

  • Module 4: Implementation of Digital Circuits (CMOS Logic)

  • Module 5: Combinational Logic Design

  • Module 6: Sequential Logic Design

  • Module 7: Building blocks of a modern computer

  • Module 8: Modern-day digital design (trends, technologies and practices)

Lab Topics

  • Hardware Description Languages and Tools

  • Basics of VHDL

  • Combinational Logic Design

  • Sequential Logic Design

  • System design

Evaluation (weightage)

  • Quizzes (15%)

  • Assignments (10%)

  • Lab exercises (30%)

  • Exams (45%)